Tensilica has proudly announced by its face intensive computing data plane and DSP (data signal processor) such as imaging, video, Internet and cable/wireless baseband communications processor IP consolidate its leader in the areas of the IP core position, any need huge data processing applications will greatly benefit from these breakthroughs are Tensilica -- through built-in functions for the LX4 data Xtensa SOC ® DPU) can plane processor (data bandwidth improve these application 4 times!

New Xtensa LX4 DPU support higher local data storage bitwidth, highest to each cycle 1024 bits, support wider 128-bit VLIW (ultra-long instruction word) command, thus improve instruction parallel. New cache prefetching function, can be in piece external storage under the condition of the time delay high help improve the system performance, Tensilica will have these technology is applied to the latest release for LTE ConnX BBE64 DSP communications.
"Tensilica DPUs advantage is also with control and signal processing ability, with a standard RISC or DSP core can be compared, optimizing ascension 10-fold to 100 times!" Tensilica marketing and business development vice President Steve Roddy points out, "now, after a Xtensa LX4 Tensilica can provide, the IP kernel ranging from tiny programmable DPU 28nm technology in the 1GigaMAC DSP ability mm2 0.01) to provide the highest performance of the industry may authorize DSP core BBE 64 - ConnX 128, its ability to deal with more than 100 per GigaMAC!"

For high bandwidth applications have wider access to data ability
And the Tensilica Xtensa LX3, compared LX4 DPU Xtensa DPU have 4 times local storage bandwidth, each cycle can be completed in 2 512 most a access operations, stylist can now easily realize super wide SIMD (single instruction multiple data), it could put more DSP for MAC (by data also add operation), make each clock cycle, which makes performance greatly ascend Xtensa LX4 DPU particularly suitable for wired and wireless baseband processing, video pretreatment and post-processing, image signal processing and various network packet processing applications.

In addition to the above local memory bandwidth enhancement, Tensilica existing customizable local port and queue can provide almost unlimited point-to-point data and control signal bandwidth. Tensilica now can provide in Xtensa DPU and other system module as RTL module establish internal interconnection between the port and queue, also can provide new ultra-high bandwidth local memory interface.

Provide wider instruction enhanced parallel processing ability
Have Xtensa LX4, Tensilica can let its FLIX (flexible length instructions commands expand) instructions from double length, 64-bit extensions to 128-bit per clock cycle, this makes the operation quantity can be completed in double Xtensa FLIX instructions, and basic instruction set seamless mix, so when in use FLIX without very troublesome to switch mode.

The Xtensa LX4 DPU FLIX instructions and traditional VLIW DSP, can provide compared in very high performance and reduce the volume and Xtensa Tensilica code of C/C + + compiler can infer from the source code and automatic parallelism, multiple different operating parallel into a FLIX instructions. A Xtensa FLIX instructions with LX4 DPU to very low clock frequency running parallel operation, it provides with the performance can clock frequency higher bigger than comparable VLIW chip, while in kernel complete the same tasks more low power it!

Access to reduce cycle gets counted
New data prefetching before use in data for operation in advance to the data, so take GaoYanChi system can reduce the number of execution cycles, so that when the application code need, data is ready, DPU must wait in data, can reduce the waste of clock cycle. When the data flow is stored address from neighboring when this advantage is more outstanding, compared to add a independent DMA (direct memory access) engine, for example, it is a more simple method of optimal memory access. It does not need additional software programming and the application code adjusted.

The key to success: automation
Use Tensilica development tools, not only can automatically generate DPU hardware, also can generate the complex software tools matching, because all the Xtensa chain include a set of processor to the same basic instruction set, so based on the basic instruction set of 3rd party application software can be run on all Xtensa processor, even after Xtensa DPU depth of custom.

Customizable DPU Xtensa with mainstream operating systems, DEBUG and ICE (online simulators) solutions are compatible, each XtensaDPU are automatically generated complete software tools chain, including an Eclipse framework based on the advanced integrated development environment, a world-class compiler, a cycle of precise and compatible SystemC instruction set simulators and complete industrial standard GNU tools chain.
Along with the release of Tensilica vector and auxiliary tool, this is a pioneering tool, it give developers to provide advice to improve their operation SIMD (single instruction in how data) on the C code DSP programming style, the vector change auxiliary tools can point out what code hampered the compiler for vector optimization, so the software can hair person can improve, thus giving full play to the C source code DPU side-by-side execution advantage.

Tensilica now can provide Xtensa LX4 DPU IP, in Xtensa LX4 45nm process basic DPU clock frequency can exceed 1 GHz, and size only mm2 0.044.